Among the requirements of variety of microelectronic circuit components and systems, such as those deployable in harsh (spaceborne) operating environments, are the need for the circuit-containing modules to be hermetically sealed and to have a high packing density (minimum volume). For this purpose, the integrated circuit chip packaging industry has developed a number of `edge`-connected multi-chip assembly architectures through which a plurality of leadless chip carriers (LCCs) or a plurality of semiconductor (silicon) dies are arranged in a stacked configuration on a printed wiring board and interconnected by means of some form of thin film metallization or tape automated bonding (TAB) lead structure that extends across the aligned edges of the stack. Examples of these packaging schemes (such as those employed for the packaging of silicon memory chips) include vertical post and flat pack style LCC stacks developed by Dense-Pac Corporation, Garden Grove, Calif., `Stacked TAB` devices produced by Matsushita Corp., Japan, and a variety of three-dimensional `cubes` proposed by Texas Instruments and Irvine Sensors.
A problem with each of these packaging architectures is their complexity and significant expense of manufacture, in particular the high cost of formation of a thin film metallization along the sides or edges of the stacked components (either LCCs or the silicon die themselves), and the cost and volume of additional structure required to house an interconnected stack in a hermetically sealed package.